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TLC5510
- 基于VHDL语言，实现对高速A/D 器件TLC5510 控制-Based on the VHDL language, to achieve high-speed A/D control devices TLC5510
abc
- 本软件设计D触发器的目的和任务：1.使学生全面了解如何应用该硬件描述语言进行高速集成电路设计；2.通过软件使用、设计与仿真环节使学生熟悉EDA-VHDL开发环境；3. 通过对基本题、综合题的设计实践，使学生掌握硬件系统设计方法（自底向上或自顶向下），熟悉VHDL语言三种设计风格，并且培养学生应用VHDL语言解决实际问题的能力。 -The software design of D flip-flop of the purpose and tasks: 1. To enable students t
suocunqi
- Ｄ锁存器ＶＨＤＬ语言描述。使能端有效时，Ｑ《＝Ｄ-D latch described in VHDL language. Enable effective end when, Q " = D
adc5510
- 使用VHDL语言编写的A/D转换程序，可在FPGA平台使用-Using the VHDL language in the A/D conversion process can be used in the FPGA platform
d_flipflop
- this is a general d-flip flop design in vhdl.
zonggongcheng
- 三个结合起来的D触发器的vhdl，分别是电平触发，上升沿出发和下降沿出发。-Combining the three D flip-flop vhdl, respectively, trigger level, rising and falling edge start start.
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
d_flip_175
- 4 D-FlipFlop source code with VHDL
dff
- 用VHDL语言编写的带进位、置位、复位的D触发器，异步清零D触发器，同步清零D触发器-library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity exp7_10 is port( clk: in std_logic d: in std_logic clr: in std_logic en,s:in std_logic q: o
d_ff
- 带置位、清零使能的D触发器以及同步清零D触发器、异步清零D触发器-VHDL，DFF
2dFIR
- 2 D FIR filter With VHDL-2-D FIR filter with VHDL
FIFO
- 这是用VHDL设计的一个8*9阵列的D触发器组成FIFO（first in first out）-This is a VHDL design using an 8* 9 array of D flip-flop composed of FIFO (first in first out)
project6_source
- VHDL D_Flip-Flops D Flip-Flop P/C layout and results of verification.
adc
- 掌握S3C2410A的模/数(A/D)转换器的应用设置，进行电压信号的测量.使用AIN0和AIN1测量两路直流电压，并将测量结果通过UART0向PC机发送.-NC divider based on VHDL language, the designer can modify the frequency coefficient code
f_add
- EDA实验中的全加器的VHDL语言的实现，包含半加器、全加器、JK触发器、D触发器以及50m分频的源程序-EDA test full adder in VHDL language implementation, including the half adder, full adder, JK flip-flop, D flip-flop and the frequency of the source 50m
lab2
- D-type storage elements The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops. Write a VHDL file that instantiates the th
LCD
- 实现vhdl语言中的一系列功能和方式方法。具体的功能是lcd实现的编译和仿真。-it can do d function as lcd.
DFF1
- 较好的D触发器VHDL代码，欢迎大家下载交流，学习。-good D vhdl date,wolcom to use.
digital-storage-oscilloscope
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形-The problem to design a digital storage oscilloscope, to Xilinx, Inc. 200,000 FPGA chip as the core, supplemented by the necessary peripherals (incl
New-folder
- Vhdl codes for D flip flop and so